Many computers use read-modify-write cycles for certain purposes, especially microcontrollers (.mu.C). A common application is to implement a bit instruction, for example, to clear or set a bit stored in a register or port. To implement this capability, a series of instructions are provided that will read, say, a port and will also read the value stored in a latch, possibly change it, and then rewrite it to the latch. These instructions can, for example, read a port byte, all 8 bits, modify only one addressed bit, and then write the new byte back to the latch.
Many popular .mu.Cs employ an interrupt system in control applications typically to, for example, toggle a port pin, or reload a timer, or read data presented at a port by a peripheral data-collecting hardware device. This interrupt system typically operates by the peripheral device or internal timer (herein referred to as "hardware" or "peripheral unit") setting a bit to serve as a flag in a register dedicated to that purpose. The term "register" is used in the widest sense to mean any kind of device capable of storing a bit, including memory locations dedicated to register functions as well as flip-flops (FF), which are commonly used as latches to store a one bit message. The CPU part of the .mu.C will poll these registers and upon finding a set bit that indicates that certain hardware needs attention, will then stop its normal processing and branch to an interrupt service routine especially designed to handle that particular hardware. When such a flag is set representing an interrupt, it is important for the .mu.C to service that interrupt; therefore it is important that the state of the register containing an interrupt flag is not changed until the interrupt is processed. In general, the problem exists with any register storing a status bit that represents the status of hardware, internal or external, and that must not be changed until the computer is able to take an appropriate action.
However, as noted above, when a read-modify-write operation is executed, one of its functions is to read certain latches, modify a bit stored in the latch, and rewrite it to the latch. Thus, if during a read-modify-write cycle, hardware happens to modify a bit to, say, a "1" in its latch, the read-modify-write cycle might read the bit, clear it, and write back a "0" to the latch before the CPU has had an opportunity to read the set bit and enter a service routine, since the CPU while it is executing the read-modify-write instructions cannot poll the registers for interrupts.
In certain popular .mu.Cs the solution to this problem of protecting hardware-modifiable status bits involves the provision of complex clock phases with register updates restricted to particular clock phases to avoid conflicts. Other suggested schemes involved the use of a shadow register to store the modified data and then to use the stored contents to update the register after the write-back phase of the read-modify-write cycle is completed. But this solution requires an undue increase in chip die area for the additional circuitry needed to implement this solution.